Bit-serial digital signal processing is known to be efficient, from the standpoint of the amount of digital hardware required, for computing fixed algorithms involving multiplication and addition processes. However, when programmable algorithms are to be employed, or when considerable memory is involved in carrying out an algorithm, as in a general-purpose computer or in a microprocessor, electronic designers have used bit-parallel processing instead of bit-serial digital signal processing.
Data acquisition systems for generating digital data for the purposes of computation may receive analog input signals from a plurality of sensors, which analog signals must be digitized before they can be used by a computer as a basis for supporting computations. It is desirable to include respective analog-to-digital converters for the analog output signals from the various sensors within the confines of an inexpensive single monolithic integrated circuit, together with some simple initial processing circuitry. Such data acquisition circuitry can be constructed using metal-oxide-semiconductor (MOS) integrated circuit technology and is suited for applications such as power metering and internal-combustion engine control.
Since the unit cost of monolithic integrated circuits tends to go up with the complexity of the digital hardward within their confines, analog-to-digital converters, multiplexers, and digital signal processors that are economical of the digital hardware involved were particularly considered by the inventor and his co-workers. Bit-serial multiplexers and processors are particularly economical of digital hardware; and an interconnection for a bit-serial signal requires but two lines, one line for conducting the serial flow of data bits, and the other line for conducting parsing signals. The speed requirements upon a digital signal processor in a data aquisition system are often not so onerous but that bit-serial computations are likely to be found to be fast enough. Oversampling analog-to-digital converters of sigma-delta type, particularly those with first-order sigma-delta modulators, are economical of digital hardware.
The use of a plurality of oversampling analog-to-digital converters of sigma-delta type introduces the need for a plural-channel decimation filter. There is a desire to use sinc.sup.2 digital filtering, in which the kernel is a sampled-data representation of a triangular time-domain response, to achieve sufficient selectivity against harmonic components of the sinusoids being filtered, and at the same time to keep filter latency reasonably short.